1. Field of the Invention
The present invention relates to a high resolution, fully differential CMOS comparator utilizing a high gain, fully differential operational amplifier and an output latch and wherein the necessary control of the output common mode voltage of the high gain operational amplifier is implemented in a particularly effective way without using a dedicated output common mode control circuit.
A comparator must "detect" whether a varying signal Vin is larger or smaller than a fixed signal Vref, commonly referred to as the threshold voltage of the comparator, as schematically shown in FIG. 1. In other words, if Vin&gt;Vref, the output signal of the comparator Vout must be, e.g. a logic "1", while if Vin&lt;Vref, the output signal Vout must be a logic "0". Indicative of the resolution of the comparator is the minimum difference (Vin-Vref) which the comparator is capable of correctly detecting. Obviously the ultimate limitation for resolution is represented by the electronic noise intrinsic to the comparator circuit, however the basic limitation is in practice determined by the offset voltage of the comparator, as well known to the skilled technician, which may have a value of up to about 10 mV. In order to make high resolution (.ltoreq.100 .mu.V) comparators it is necessary to cancel the offset by means of additional circuitry and to reduce as much as possible the electronic noise by using low noise input stages.
2. Description of the Prior Art
In CMOS technology, where it is relatively easy to form capacitors and integrated switches, the most used solution for cancelling the offset is that of storing the Vref less the offset voltage (Vof) in a capacitance (C) during an operating phase immediately preceding the phase of comparison between the input signal and the threshold voltage (FIG. 2a). In this way, during the successive comparison phase (FIG. 2b), an effective cancellation of the offset is achieved. In fact when Vin=Vref, the Vx voltage present at the inverting (-) input terminal of the comparator is equal to Vof, thus the two input terminals of the comparator are at the same potential and therefore if Vin&gt;Vref, Vx&gt;0 so that the comparator's output commutes in a direction and if Vin &lt;Vref, Vx&lt;0 so that the comparator's output commutes in an opposite direction.
Comparators of this kind have a respectable but not extremely high resolution because this solution introduces an additional error factor due to the injection of charge in C by the integrated switch SWI when the latter switches from an (a) condition to a (b) condition; (Re: "Precision Variable Supply CMOS Comparator"--IEEE Journal of Solid State Circuits, Vol. SC-17, No. 6, December 1982).
For high precision comparators it is customary to cancel the offset by means of the above described switched capacitance input circuitry and to cancel or in any case reduce drastically the charge injection by the switch in the capacitor by reproducing on the noninverting input the same circuitry which is connected to the inverting input, as shown in FIGS. 3a and 3b. In this way in fact the charge Q.sub.SW1A injected by the switch SW1A in the capacitor C.sub.A, which consequently develops on the inverting input an error voltage given by Q.sub.SW1A /C.sub.A, is in a first approximation equal to the charge injected by the switch SW1B in the capacitor C.sub.B, which consequently develops on the noninverting input a similar error voltage given by Q.sub.SW1B /C.sub.B, thus the inputs of the comparator are subject to common mode shifting but not to a differential shift and therefore, being the comparator sensitive only to a difference of voltage between the inputs, an error caused by an injection of charge is not developed.
Because of the extremely high gain requirement (for input signals of about 100 .mu.V output signals of about 10V must be obtained), it is common to form a comparator by utilizing several cascaded amplifying stages, each provided with its own circuit for cancelling its offset voltage, followed by a terminal latch circuit. The final latch stage, being a positive feedback circuit, is used for relaxing open-loop gain specifications of the amplifying stages, for which the only function becomes that of bringing the level of the minimum input signal which must be detected to a level such as to be greater in terms of absolute value than the offset voltage of the final latch circuit, an offset which cannot be cancelled, as it is well known to the skilled technician. By considering that in the worst of cases this offset may be of about 30 mV to 40 mV, for a lowest input signal level of 100 .mu.V a gain of the single amplifying stage or of the cascaded amplifying stages which precede the final latch circuit of about 400 is needed.
The simplest solution is that of utilizing a single high gain amplifier (e.g. with a gain of about 1000) followed by a common latch circuit, as shown in FIG. 4, and where there is always a storing phase (a) of the amplifier offset and a comparison phase (b) of the signal Vin with the voltage Vref. The main problem of this solution is the fact that the amplifier, when the latter is of a fully differential type as it is often the case in MOS circuits as shown in FIG. 4, needs a dedicated circuit for stabilizing the output common mode voltage, as it is well known to the skilled technician (Re: "A Family of Differential NMOS Analog Circuits for a PCM Coded Filter Chip"--IEEE Journal of Solid State Circuits, Vol. SC-17, No. 6, December 1982); this special circuit for stabilizing the common mode is burdensome in terms of overall layout of the integrated circuit but above all it strongly loads the output of the amplifier during the comparison phase (b), so that the amplifier becomes relatively slow to react to an input signal and consequently the comparator takes a relatively much longer time to produce the result of the comparison at its output terminal.
Another known solution is that of using low gain (e.g. with a gain of about 10 to 20), fully differential amplifiers connected in cascade because these amplifiers do not need an output common mode stabilizing circuit as they exert this control automatically (Re: "A High Speed, High Precision Comparator Design for a 10 bit 15 MHz A-D Converter" memorandum No. UCB/ERL M85/86, Aug. 7, 1985, Electronics Research Laboratory, College of Engineering, University of California, Berkeley).
The main drawback of this other known solution is the fact that at least three or more operational amplifiers are generally needed, each of them being provided with respective switched capacitance input circuits for cancelling the respective offsets and therefore there is a remarkable burden in terms of layout, as it is evident from the block diagram shown in FIG. 5, in respect to the earlier solution using a single high gain amplifier shown in FIG. 4.
A typical example of a fully differential, high gain amplifier having a circuit for stabilizing the output common mode, which is used, according to the current technique, for making comparators of the type described in relation to FIG. 4, is depicted in FIG. 6. Essentially the fully differential, high gain amplifier is of the so-called "folded cascode" type and is formed essentially by transistors M1, M2, . . . M10, M11 and M12. As it will be evident to the technician, the circuit for controlling the output common mode voltage is depicted within the two dash line squares A and B (for the output OUT+ and for the output OUT-, respectively). The circuit senses whether the common mode voltage or the half-sum of the voltages present at the two output terminals OUT+ and OUT- is different from the ground potential and consequently intervenes on the gates of the two MOS transistors M11 and M12 of the amplifier so as to modify the respective bias currents in order to return the common mode voltage of the two outputs near the ground potential of the circuit.
By contrast, a typical example of a fully differential, low gain amplifier which is used for forming the chain of cascaded amplifiers of a comparator made according to the block diagram depicted in FIG. 5, is shown in FIG. 7. Also in this case the structure of such a differential amplifier is familiar to the technician and does not require any particular description.